Hardware implementation of autonomous probabilistic computers
Ahmed Zeeshan Pervaiz
10.25394/PGS.10084628.v1
https://hammer.figshare.com/articles/Hardware_implementation_of_autonomous_probabilistic_computers/10084628
<pre><p>Conventional digital computers are built using stable deterministic units known as "bits".
These conventional computers have greatly evolved into sophisticated machines,
however there are many classes of problems such as optimization, sampling and
machine learning that still cannot be addressed efficiently with conventional
computing. Quantum computing, which uses q-bits, that are in a delicate
superposition of 0 and 1, is expected to perform some of these tasks
efficiently. However, decoherence, requirements for cryogenic operation and
limited many-body interactions pose significant challenges to scaled quantum
computers. Probabilistic computing is another unconventional computing paradigm
which introduces the concept of a probabilistic bit or "p-bit"; a robust
classical entity fluctuating between 0 and 1 and can be interconnected
electrically. The primary contribution of this thesis is the first experimental
proof-of-concept demonstration of p-bits built by slight modifications to the
magnetoresistive random-access memory (MRAM) operating at room temperature.
These p-bits are connected to form a clock-less autonomous probabilistic
computer. We first set the stage, by demonstrating a high-level emulation of
p-bits which establishes important rules of operation for autonomous
p-computers. The experimental demonstration is then followed by a low-level
emulation of MRAM based p-bits which will allow further study of device
characteristics and parameter variations for proper operation of p-computers.
We lastly demonstrate an FPGA based scalable synchronous probabilistic computer
which uses almost 450 digital p-bits to demonstrate large p-circuits.</p>
</pre>
2019-10-31 12:45:26
Probabilistic Computing
stochastic neural network
MRAM
optimization problems