Test Generation and Resynthesis Procedures for Test and Diagnosis Quality
2019-10-16T18:58:28Z (GMT) by
Testing and diagnosis are performed to detect and identify manufacturing failures in integrated circuits. In this dissertation, we focus on three important issues in test and diagnosis. The solutions to these issues are implemented using commercial EDA tools. No modification to the commercial tools is required. Thus, they can be easily applied to complex designs with state-of-the-art features. We first address overtesting of delay faults. Overtesting may occur when the circuit is brought into states that cannot be reached during functional operations. We address this issue by generating functional broadside tests using reachable states as scan-in states. Next, we address the issue of improving the resolution of multiple-defect diagnosis by ignoring certain tests. A feature of commercial defect diagnosis tools is used to avoid losing accuracy. Last, we address the issue of avoiding undetectable faults that model potential systematic defects caused by design-for-manufacturability (DFM) guideline violations in a cell-based design. We demonstrate that these undetectable faults tend to cluster in certain areas of the circuit, resulting in circuit areas with low coverage. The missing tests may allow detectable defects in these areas to escape detection. This can impact the defective-parts-per-million (DPPM) and reliability significantly since the defects are likely to be systematic. We address this issue in a cell-based design by eliminating the undetectable faults related to DFM guidelines that are internal and external to cells. We first propose a logic resynthesis procedure to eliminate large clusters of undetectable faults that are internal to cells. Next, we propose a layout resynthesis procedure that eliminates undetectable faults external to cells by making fine changes to the layout so as to fix the corresponding DFM guideline violations.